The present invention relates to integrated circuit memory devices and more specifically to a dynamic random access memory cell structure and a fabrication method therefor.
According to xe2x80x9cMoore""s Lawxe2x80x9d as it is popularly known, the scale of integrated circuit (IC) density has historically doubled once about every 18 to 24 months. IC manufacturers recognize a need to continue increasing the scale of integration at this pace. Manufacturers have not been able to achieve the necessary increase in density merely by using sharper photolithography techniques to linearly shrink the size of features on an IC. Other changes have had to be made, as only some features can be scaled linearly from one IC generation to the next, while other features can be scaled only by a fraction of the reduction in lithographic scale.
Features formed within the first few levels of the semiconductor surface of a wafer are conveniently measured in units of minimum lithographic feature size F or minimum lithographic dimension F. The minimum lithographic dimension F is defined as the smallest unit of length for which a feature can be defined by a photolithographic process of exposing a photoresist resist layer on the wafer through a mask, developing the resist, removing either the developed or undeveloped portions of the resist, and then etching the areas of the wafer that are uncovered.
A manufacturer selects a minimum feature size as a xe2x80x9cground rulexe2x80x9d for each generation of ICs to be produced. The ground rule is determined in consideration of the many elements of the photolithographic process: mask fabrication, illumination sources, optical elements between the illumination source and the wafer, and the properties of the photoresist, as well as the precision of the most critical etch step to be performed. Determination of the ground rule must also necessarily take into account the reliability of the photolithographic process to define features over the desired extent of the wafer, and to operate without error over the desired maintenance cycle of the process equipment. After the ground rule has been selected for a particular generation of ICs, no feature can be defined by the photolithographic process any smaller than that ground rule. As used herein throughout, the terms xe2x80x9cminimum feature size Fxe2x80x9d and xe2x80x9cminimum lithographic dimension Fxe2x80x9d are refer to a selected ground rule as described herein.
A DRAM cell structure that is reduced in size in relation to minimum lithographic dimensions is particularly advantageous because it provides a greater increase in the scale of integration than a mere reduction in the ground rule. In addition, even when no reduction is made in the minimum lithographic dimension F for a particular generation of ICs, a substantial reduction in the area occupied by the DRAM cell, in terms of minimum lithographic dimensions (F2), could provide the increased scale of integration needed to keep pace with Moore""s Law.
Some existing deep trench DRAM cell designs, such as those described in U.S. Pat. Nos. 5,264,716 and 5,360,758, incorporate a polysilicon filled deep trench as a storage capacitor which is conductively connected by a deep trench outdiffusion known as a buried strap to the drain of an insulated gate field effect transistor (IGFET) located within a shallow well just below the surface of a monocrystalline silicon substrate. In such structures, the edge of the outdiffusion from the buried strap lies very close (usually less than the minimum lithographic dimension F) to the channel region of the IGFET). In addition, because of the way the buried strap is formed by outdiffusion of dopant ions from inside the deep trench, the outdiffused doping profile extends a direct path from the trench to the channel region. The proximity of the strap and the trench to the channel region of the IGFET tends to decrease the threshold voltage VT of the n-type IGFET of such memory cells. To restore the threshold voltage Vt to the desired level, the shallow well in which the IGFET is located is implanted with ions to high dopant concentrations. However, the high well dopant concentration greatly increases the junction leakage, subthreshold voltage swing and the substrate sensitivity of the IGFET.
The article by T. Ozaki et al. entitled xe2x80x9c0.228 um2 Trench Cell Technologies with Bottle-Shaped Capacitor for 1 Gbit DRAMs,xe2x80x9d IEDM Digest of Technical Papers, 1995, pp. 661-664 (xe2x80x9cthe Ozaki et al. Articlexe2x80x9d) describes a proposed DRAM cell design which has dimensions of 6F2. That proposed cell design is similar to the deep trench DRAM cell designs described above in that the conductive path from the deep trench storage capacitor through the transfer device to the bitline-contact is essentially a straight line, except that the design described in the Ozaki et al. Article requires a surface strap rather than a buried strap.
In order to achieve the small cell size, the design described in the Ozaki et al. Article requires the edge of the deep trench storage capacitor to be placed very close to the gate conductor which controls the transfer device of the cell. Consequently, errors which occur in the positioning of masks which define the deep trench and the gate conductor (even those which are within overlay tolerances) can substantially decrease the channel width and/or prevent the surface strap between the deep trench and the channel from forming. Consequently, existing process tolerances place great obstacles to the implementation of the design described in the Ozaki et al. Article. In addition, the high probability of such channel shortening errors requires high well dopant concentrations to overcome the expected short channel effects which, as described above, leads to undesirable device degradation. As the integration density increases, a new structure is needed by which the strap and trench regions of the memory cell are further removed from the channel region of the IGFET. In that way, dopant concentrations in the IGFET can be reduced, thereby reducing the junction capacitance and improving device characteristics.
Commonly-assigned U.S. patent application Ser. No. 09/007,906, U.S. Pat. No. 6,069,390, filed Jan. 15, 1998 entitled xe2x80x9cSemiconductor Integrated Circuitsxe2x80x9d describes a self-linking active semiconductor device structure which is formed in a substantially continuous mesa region. A FET such as the device described in the above incorporated patent application, Ser. No. 09/007,908, U.S. Pat. No. 6,177,299, can be fabricated in the mesa region as the active semiconductor device, for example. This patent application is hereby incorporated herein by reference.
Commonly-assigned U.S. patent application Ser. No. 09/007,906, U.S. Pat. No. 6,069,390, filed Jan. 15, 1998 entitled xe2x80x9cSemiconductor Integrated Circuitsxe2x80x9d describes a self-linking active semiconductor device structure which is formed in a substantially continuous mesa region. A FET such as the device described in the above incorporated patent application, Ser. No. 09/007,908, U.S. Pat. No. 6,177,299, can be fabricated in the mesa region as the active semiconductor device, for example. This patent application is hereby incorporated herein by reference.
Accordingly, it is an object of the invention to provide a cell structure for a DRAM which occupies reduced area of the wafer surface in terms of minimum lithographic dimensions.
Another object of the invention is to provide an ultra compact DRAM array structure.
Still another object of the invention is to provide a method of fabricating a DRAM cell and related support devices by a single unified process.
Another object of the invention is to provide a structure for a DRAM memory cell in which the separation is proportionately increased between the strap and the channel region of the access transistor.
Another object of the invention is to provide a cell structure for a DRAM by which dopant concentrations within the IGFET device can be reduced in relation to the case where the strap is very close to the channel.
Another object of the invention is to provide a cell structure for a DRAM which has reduced junction capacitance.
These and other objects are provided by the semiconductor memory cell of the present invention. Accordingly, a semiconductor memory cell constructed according to the invention includes a storage capacitor formed in a trench etched into a substrate, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the deep trench, a buried strap conductively connecting the transfer device to the storage capacitor, wherein the transfer device includes a controlled conduction channel located at a position of the arc removed from the buried strap.
Preferably, the controlled conduction channel is located at a position which does not present a straight line conduction path to the buried strap. Preferably, the transfer device is of the insulated gate field effect transistor (IGFET) type, having a pair of source drain regions connected the buried strap and to a bitline contact, respectively, and a channel region which forms the controlled conduction channel.
In a preferred embodiment, the strap and the bitline contact are conductively connected to the mesa region at positions of the arc which are located across the trench from each other.
Importantly, the area occupied by the cell on a substrate is preferably 4.5 F2 or less, wherein F is defined as minimum lithographic feature size. In addition, it is preferred that this advantage be realized when the area occupied by the deep trench is greater than or equal to about F2.
Another preferred embodiment of the invention is a semiconductor cell array structure including a group of semiconductor memory cells each having a storage capacitor formed in a trench and a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the deep trench, wherein the mesa region conductively connects the storage capacitor to a bitline contact, and a shallow trench isolation (STI) region partially overlays each trench and forms a surface over which a gate conductor is deposited.
The present invention is also embodied in a method of forming a semiconductor memory cell, which includes the steps of:
forming a storage capacitor in a deep trench etched into a substrate including a monocrystalline semiconductor;
forming a shallow trench isolation (STI) region at least partially overlaying the deep trench;
forming and outdiffusing a strap in a sidewall of the deep trench;
forming first spacers on exterior surfaces of the STI region and deep trench;
etching, selective to the monocrystalline semiconductor;
removing the first spacers to expose a mesa region of monocrystalline semiconductor located on exterior sidewalls of the deep trench and STI region and conductively connected to the strap; adjusting dopant concentrations in at least a portion of the mesa region to form a channel region and source/drain regions;
forming a gate dielectric over at least the channel region; depositing a gate conductor over the channel region; and forming a bitline contact to a first of the source/drain regions.
Preferably, the fabrication method further includes the steps of forming second spacers on exposed sidewalls of the first spacers; and prior to removing the first and second spacers, growing a field oxide over exposed surfaces of the semiconductor material.
In addition, the method preferably further includes the step of implanting dopant ions in locations of the substrate where the field oxide is grown.
The step of forming and outdiffusing a strap preferably includes the steps of etching an upper portion of the storage capacitor including a dielectric sidewall of the storage capacitor, refilling the etched portion with a highly doped fill material; and outdiffusing dopant ions from the highly doped fill material into a region of the substrate outside the deep trench.
Finally, the source/drain regions are preferably formed in portions of the mesa region located on first and third exterior sidewalls of the union of the deep trench and the STI region, and the channel region is formed in a portion of the mesa region located on a second exterior sidewall, wherein the first and second sidewalls are contiguous and the second and third sidewalls are contiguous.
The invention is also embodied in a method of forming a plurality of memory cells in a semiconductor memory array, which includes the steps of forming storage capacitors in a deep trench etched into a substrate including a monocrystalline semiconductor; forming a shallow trench isolation (STI) region at least partially overlaying each deep trench of a group of deep trenches; forming and outdiffusing a buried strap in a sidewall of each deep trench; forming first spacers on exterior surfaces of the STI region and the deep trenches; etching, selective to the monocrystalline semiconductor; removing the first spacers to expose a mesa region of monocrystalline semiconductor located on exterior sidewalls of the union of the deep trenches and the STI region and conductively connected to each said buried strap; dividing the mesa region into discontinuous parts such that each part is connected to at most two buried straps; adjusting dopant concentrations in at least a portion of the mesa region to form a transfer device for each deep trench, each transfer device having a channel region and source/drain regions; forming a gate dielectric over at least the channel regions; depositing a gate conductor over the channel regions; and forming a bitline contact to respective ones of the source/drain regions.
In this embodiment, the step of dividing is preferably performed by applying a trim mask and etching areas defined by the mask.